Neha Paras
Assistant Professor
Centre/School/Special Centre
Special Centre for Nanoscience
Room No
109
Off. Phone
011-26749140
Email
nehaparasrao@mail.jnu.ac.in, neharao1993@gmail.com
Personal Webpage
Qualifications
PhD (Low Power VLSI Devices, 2020), National Institute of Technology (NIT), Kurukshetra, India
M.Tech. (Microelectronics and VLSI Design, 2016), Electronic Science Department, Kurukshetra University, India
B.Tech. (Electronics and Communication engineering, 2014), Kurukshetra University, India
Areas of Interest/Specialization
VLSI Design, Nanoelectronics and Bioelectronics
Experience
Assistant Professor, SCNS, JNU, New Delhi (May 2023 – Till Date)
Assistant Professor, NIT Delhi (Jan 2022 – April 2023)
Assistant Professor, PEC Chandigarh (Sept 2021 – Dec 2021)
Assistant Professor, NIT Jalandhar (Jan 2021 – June 2021)
Awards & Honours
Qualified UGC NET (Electronic Science) 2020
SERB DST Travel Grant (Los Angeles, USA) 2019
MHRD PhD Fellowship (2017)
International Collaboration/Consultancy
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Best Peer Reviewed Publications
- Billel Smaani, Neha Paras, Shiromani Balmukund Rahi, Young Suh Song, Ramakant Yadav, and Subham Tayal, “Impact of the Self-Heating Effect on the Nanosheet FET Performance” ECS Journal of Solid State Science and Technology, Vol. 12, 021005, PP: 1-18, (2023), IOP Science. (ISSN:2162-8777) (DOI: 10.1149/2162-8777/acb96b), Scopus, IF: 2.07, HI: 56.
- Jeetendra Singh, Shailendra Singh and Neha Paras, “Design and Integration of Vertical TFET and Memristor for Better Realization of Logical Functions,” Silicon, Vol. 14, (2022) Springer. (ISSN: 1876-9918). (DOI: 10.1007/s12633-022-02047-1) SCI, Scopus, IF: 2.941, HI: 34.
- Deepika, Neha Paras, Anil Arya, Rajesh Kumar, Shashi Sharma, Sohan Lal, V. Kumar and Anurag Gaur, “Room temperature magento-electric coupling in Pb-Zn substituted Co2Y-hexaferrite,” Journal of Materials Science: Materials in Electronics, Vol. 33, No. 18, (2022), Springer. (ISSN: 0957-4522) (DOI: 10.1007/s10854-022-08561-7) SCI, Scopus, IF: 2.478, HI: 80.
- Neha Paras and S. S. Chauhan, “Temperature sensitivity analysis of vertical tunneling based dual metal Gate TFET on analog/RF FOMs,” Applied Physics A: Materials Science & Processing, Vol. 125, No. 5, 317, (2019), Springer. (ISSN: 1432-0630). (DOI: 10.1007/s00339-019-2621-x), SCI, Scopus, IF: 2.983, HI: 149
- Neha Paras and S. S. Chauhan, “A novel vertical tunneling based Ge-source TFET with enhanced DC and RF characteristics for prospect low power applications,” Microelectronic Engineering, Vol. 217, 111103, (2019), Elsevier. (ISSN: 0167-9317) (DOI: 10.1016/j.mee.2019.111103), SCI, Scopus, IF: 2.662, HI: 99
- Neha Paras and S. S. Chauhan, “Insights into the DC, RF/Analog and linearity performance of vertical tunneling based TFET for low-power applications,” Microelectronic Engineering, Vol. 216, 111043, (2019), Elsevier. (ISSN: 0167-9317) (DOI: 10.1016/j.mee.2019.111043), SCI, Scopus, IF: 2.662, HI: 99
- Neha Paras and S. S. Chauhan, “Vertical Tunneling Based Tunnel Field Effect Transistor with Workfunction Engineered Hetero-Gate to Enhance DC Characteristics,” Journal of Nanoelectronics and Optoelectronics, Vol. 14, No.1, (2019), American Scientific Publishers.(ISSN: 1555-1318) (DOI: 10.1166/jno.2019.2427), SCI-E, IF: 1.069, HI: 23
Recent Peer Reviewed Journals/Books
- Neha Paras, Shiromani Balmukund Rahi, Abhishek Kumar Upadhyay, Manisha Bharti, Young Suh Song, “Design and analysis of novel La: HfO2 gate stacked ferroelectric tunnel FET for non-volatile memory applications, Memories-Materials, Devices, Circuits and Systems, Vol. 7, 100101, (2024), Elsevier, (ISSN: 2773-0646) (DOI; 10.1016/j.memori.2024.100101).
- Pooja Raghav, Manisha Bharti, Neha Paras, “Detection of Herpes Biomolecule using Ge-based Dielectrically Modulated TFET,” International Journal of Microsystems and IoT, Vol 2, No. 10, pp. 1239-1245, (2025), (DOI: 10.5281/zenodo.14167709)
- Abhishek Kumar Upadhyay, Siromani Balmukund Rahi, Billel Smaani, Ball Mukund Mani Tripathi, Neha Paras, Ribu Mathew, Seema Rajput, Ankur Beohar, “Compact analytical model for graphene field effect transistor-Drift-diffusion approach,” Advanced MOS Devices and their Circuit Applications, CRC Press, pp. no.- 56-73, ISBN 9781032670270, (2024). DOI: 10.1201/9781032670270-5.
- Sahil Saurabh, Manisha Bharti and Neha Paras, "A Comprehensive Evaluation of Schmitt Trigger Designs in 90nm CMOS Technology," ICECSP, IEEE Xplore, 2024, (DOI: 10.1109/ICECSP61809.2024.10698593).
- Poonam Sharma, Manisha Bharti, Neha Paras, “Dynamic Power Reduction in dual edge triggered D-Flip-flop clock gating using Memristor,” ICECSP, IEEE Xplore, 2024, (DOI: 10.1109/SCEECS61402.2024.10482102).
Patents (if any)
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